How to Choose a PCB Stackup: Layer Count, Material, and Controlled Impedance

Quick Navigation

1. What Is a PCB Stackup?
2. How Many Layers Do You Actually Need?
3. Choosing the Right PCB Material
4. Controlled Impedance and the Stackup
5. Common Stackup Configurations
6. What to Tell Your Fabricator
7. Frequently Asked Questions

What Is a PCB Stackup?

A PCB stackup defines the physical layer structure of your board: the number of copper layers, the dielectric materials between them, and the thickness of each layer. It is one of the earliest design decisions you make and one of the hardest to change later. The stackup affects trace impedance, signal integrity, power distribution, EMI behaviour, and fabrication cost — all at once.

Getting the stackup right before routing begins saves significant rework. Changing it after differential pairs are routed, or after impedance-controlled traces are placed, typically means re-running your impedance calculations and adjusting trace widths across the board.

How Many Layers Do You Actually Need?

Layer count is driven by routing density, the presence of controlled-impedance signals, power plane requirements, and EMI shielding needs. More layers add cost and lead time; too few layers can make a design unroutable or force compromises on signal integrity.

Layer Count Decision Guide

When to Go from 4 to 6 Layers

• Multiple high-speed interfaces: If you have more than one high-speed interface (e.g., USB 3.0 and PCIe on the same board), 6 layers gives you dedicated routing layers for each without sharing reference planes
• BGA components: Dense BGAs often require an inner signal layer for breakout routing that cannot be achieved on outer layers alone
• Mixed signal designs: Separating analog and digital ground references becomes cleaner with additional layers
• EMI requirements: Designs subject to strict radiated emissions limits benefit from the additional shielding that inner stripline layers provide
• Routing congestion: If your 4-layer route is above roughly 70–80% completion, consider moving to 6 layers rather than compromising signal paths

Choosing the Right PCB Material

PCB material selection is mostly a question of signal loss budget, data rate, trace length, operating temperature, and cost. For most digital designs, the choice is between standard FR-4 and its enhanced variants. RF and high-speed serial designs require more careful consideration.

The two electrical properties that matter most are the dielectric constant (Dk, also written as εr) and the dissipation factor (Df, also written as loss tangent). Dk affects trace impedance and propagation velocity; Df determines how much signal energy is absorbed by the dielectric as frequency increases. Both vary across frequency, and better materials have more stable, lower values of each.

A common simplification is to frame material choice purely around frequency ("FR-4 works below X GHz"). In practice, the right question is whether your total insertion loss budget is met — which depends on trace length and data rate together, not frequency alone. A 5 Gbps signal on a 200 mm trace loses far more than the same signal on a 50 mm trace, even at the same nominal frequency content. Always evaluate material against your actual loss budget, not a frequency threshold.

Material Comparison

Material Selection by Application

Loss Breakdown: Dielectric, Conductor, and Roughness

Total insertion loss on a PCB trace has three main contributors, and their relative importance shifts with frequency:

• Dielectric loss: Caused by the Df of the laminate material. Scales roughly linearly with frequency and trace length. Dominant at higher frequencies — the primary reason to move from FR-4 to FR408 or Megtron 6 for high-speed interfaces
• Conductor loss: Resistive loss in the copper trace. Increases with the square root of frequency (skin effect). Significant at lower frequencies and on thin or narrow traces; at very high frequencies, dielectric loss overtakes it
• Surface roughness loss: As frequency increases, current concentrates on the surface of the conductor (skin depth shrinks). A rough copper surface — common on standard electrodeposited foil — increases the effective path length and raises conductor loss. Low-profile (LP) or very-low-profile (VLP) copper foils reduce this effect and are specified on high-speed laminates such as Megtron 6

When evaluating materials for high-speed designs, look at all three contributors together. Switching to a low-Df laminate while retaining standard-roughness copper foil will recover dielectric loss but not roughness loss — both need to be addressed for the best insertion loss performance at data rates above ~10 Gbps.

Controlled Impedance and the Stackup

Controlled impedance is not a property you dial in on a single trace — it is a result of the interaction between trace geometry (width, thickness), the dielectric constant of the surrounding material, and the distance to the nearest reference plane. All three are determined by the stackup. This is why stackup selection and impedance planning must happen together.

Microstrip vs Stripline

The two most common controlled-impedance structures are microstrip (trace on an outer layer, one reference plane below) and stripline (trace on an inner layer, reference planes above and below). Each has distinct characteristics:

How Stackup Parameters Affect Impedance

The relationships are straightforward in direction, even if the exact values require a field solver to compute accurately:

• Wider trace → lower impedance: More copper area relative to the reference plane reduces impedance
• Thicker dielectric (greater distance to reference plane) → higher impedance: More separation between trace and plane increases impedance
• Higher Dk material → lower impedance: A higher dielectric constant concentrates the electric field, reducing impedance
• Tighter intra-pair gap (differential) → lower differential impedance: Closer coupling between P and N lowers Zdiff

Return Path Discontinuities

Controlled impedance is only half of the picture. Every signal trace has a return current — and that return current travels in the reference plane directly beneath (or above) the trace, mirroring the signal path. When the return path is interrupted, the signal integrity degrades regardless of how well the trace impedance is controlled. This is one of the most commonly overlooked issues in high-speed PCB stackup design.

For detailed guidance on how this applies to differential pairs specifically, see our guide on differential pair routing guidelines and stackup selection.

• Via layer transitions: When a trace changes layers via a through-hole via, the return current must also find a path to the new reference plane. Without a stitching via placed within 1–2 mm of the signal via, the return current is forced to take a long detour through the plane, radiating EMI and causing impedance discontinuity at the transition point
• Plane splits: A gap or split in the reference plane forces the return current to flow around the gap — potentially across a long path. Routing a high-speed signal over a plane split introduces a significant discontinuity and is one of the most reliable ways to cause EMI failure. If a split is unavoidable, bridge it with a stitching capacitor close to the crossing point
• Reference plane changes: Routing a trace over a layer where the reference plane changes from ground to power (or vice versa) changes the return current's reference. This is manageable if the planes are well-decoupled, but should be avoided for the most sensitive high-speed signals

Common Stackup Configurations

The most widely used configurations are 4-layer and 6-layer. Both have well-established layer arrangements that balance routing, signal integrity, and cost.

4-Layer Stackup (Standard)

The most common 4-layer arrangement places signal layers on the outer surfaces with dedicated ground and power planes on the inner layers:

• Both outer signal layers have a reference plane immediately adjacent, which supports controlled impedance on both surfaces
• Ground and power planes are adjacent, which provides natural decoupling capacitance between them
• Suitable for USB 2.0, 100M/1G Ethernet, SPI, I2C, moderate-speed ARM processors on FR-4 or FR408
• Limitation: No inner signal layer; high-density BGAs may be difficult to break out

6-Layer Stackup (High-Speed)

A common EMC-friendly 6-layer arrangement places both inner signal layers between reference planes, ensuring true stripline routing for the inner layers and microstrip on the outer surfaces:

• Layer 3 is a true asymmetric stripline, sandwiched between the Ground plane on L2 and the Power plane on L4 — both act as AC reference planes for signal integrity purposes, provided the power plane is low-impedance and adequately decoupled with bypass capacitors. Without sufficient decoupling, the power plane's AC impedance rises at high frequencies and its effectiveness as a reference degrades
• Both outer signal layers (L1 and L6) are microstrip, each with an immediately adjacent reference plane — L2 for L1, and L5 for L6
• Suitable for USB 3.x, PCIe Gen1/2, DDR4, HDMI, and designs with BGA components
• Important: If you need a second inner signal layer (e.g., L4 or L5), the power plane must be reassigned and the layer arrangement revisited — placing two signal layers adjacent with no reference plane between them will compromise EMI and crosstalk performance significantly

What to Tell Your Fabricator

Clear stackup documentation prevents manufacturing errors and avoids back-and-forth that delays your build. Most fabricators have standard stackup offerings — your job is to specify which requirements are fixed constraints and which are flexible. For a broader pre-layout checklist that covers stackup alongside other design requirements, see our PCB design checklist for layout engineers.

Essential Information to Provide

• Layer count and overall board thickness: e.g., 4-layer, 1.6 mm finished thickness
• Controlled impedance requirements: List each impedance target, its tolerance, the layer it applies to, and which nets or net classes it covers (e.g., "90Ω ±10% differential on Layer 1, nets USB_DP / USB_DM")
• Material specification: Name the material or specify the electrical requirements (Dk, Df) and let the fab propose a material if you have flexibility
• Copper weight per layer: e.g., 1 oz outer, 0.5 oz inner — affects trace resistance and current capacity
• Dielectric thickness constraints: If any layer spacing is fixed (e.g., to achieve a specific impedance), call it out explicitly
• Surface finish: HASL, ENIG, OSP — relevant for solderability, shelf life, and RF performance

Impedance Callout Format

A clear impedance callout on your fabrication drawing removes ambiguity. Include it in a table on the drawing rather than relying on notes in the Gerber files alone:

Want to Know More About How We Use AI with PCB Design?

Check out our comprehensive blog covering AI-assisted PCB design verification across Altium, Cadence, KiCad and other tool series.